Recently, a semiconductor integrated circuit device has progressively downsized by adopting a surface mount type package or narrowing a pitch between terminals. Because of narrowing the pitch between terminals, adjacent terminals are easy to short-circuit owing to, for example, a presence of a dust particle having a conductive property or a solder bridge produced in packaging the terminals on a substrate. In order to prevent or find short-circuiting between adjacent terminals, additional appearance inspection may be effective after terminal packaging process is performed. Detailed visual inspection in the appearance inspection process however leads to an increase in manufacturing cost.
Patent Document 1 shows a monitor circuit for checking an electric path resulting from short-circuiting. When the monitor circuit is mounted on a substrate, the monitor circuit can check a presence of the electric path connecting adjacent terminals. The monitor circuit includes a short detection circuit for detecting the presence of the path and a state display circuit for displaying a detection result from the short detection circuit. A semiconductor apparatus disclosed in Patent Document 2 includes a short detection line for detecting an occurrence of short-circuiting. The short detection line is arranged between at least one pair of adjacent terminals. A presence of short-circuiting between terminals is checked based on variation of an electric potential of the short detection line. As disclosed in Patent Document 2, an un-connection terminal is arranged between terminals to separates the terminals.
Patent Document 1—Japanese Patent Application Publication No. 2001-66340
Patent Document 2—Japanese Patent Application Publication No. 2007-19329
FIG. 9 is a schematic circuit diagram illustrating a configuration of a series regulator with using a conventional IC (integrated circuit) 1 and arrangement of terminals of the conventional IC. The IC 1 includes a power supply circuit 3 that provides a first series regulator in cooperation with a transistor 2 mounted on a substrate. The transistor 2 functions as an output transistor. The IC 1 further includes a power supply circuit 4 that has an output transistor, and that provides a second series regulator. One circuit between the power supply circuit 3 and the power supply circuit 4 is selected to operate on the basis of a selection signal SEL, which is provided from an outside of the IC 1 via a selection circuit in the IC 1.
The IC 1 includes high potential side power supply terminals 6, 7, a low potential side power supply terminal 8, a control signal output terminal 9, a phase compensation input terminal 10, a voltage output terminal 11, and a selection signal input terminal 12. The high potential side power supply terminals 6, 7 and the low potential side power supply terminal 8 are used for supplying electric power to the power supply circuits 3, 4. The electric power energizes the power supply circuits 3, 4 to operate. The control signal output terminal 9 is used for outputting a control signal REF to a base of the transistor 2 from the power supply circuit 3. The phase compensation input terminal 10 is used for inputting a phase compensation signal from an emitter of the transistor 2 to the power supply circuit 3. The voltage output terminal 11 is used for outputting a power supply voltage Vo from the power supply circuit 4 to a power output terminal 15 via a switch 14. The selection signal input terminal 12 is used for inputting the selection signal SEL thereto. The IC has a QFP (Quad flat package) configuration for instance. As shown in FIG. 9, the terminals 6-12 are arranged in the following order: the low potential side power supply terminal 8, the phase compensation input terminal 10, the control signal output terminal 9, the high potential side power supply terminals 6, 7, the voltage output terminal 11, and the selection signal input terminal 12.
In the IC 1, during the power supply circuit 3 is selected to operate on the basis of the selection signal SEL, when the high potential side power supply terminal and the control signal output terminal 9 adjacent to each other are short-circuited, the transistor 2 is configured to forcibly switch on. As a result, an excess electric current flows to a load (not shown) through the transistor 2 and the power output terminal 15. When the low potential side power supply terminal 8 and the phase compensation input terminal 10 adjacent to each other are short-circuited, an output circuit in the power supply circuit 3 increases the control signal REF. As a result, an excess current flows to the load.
During the power supply circuit 3 is selected to operate on the basis of the selection signal SEL and the switch 14 is in an on state, when the high potential side power supply terminal 7 and its adjacent voltage output terminal 11 are short-circuited, an output voltage Vcl increases to Vcc. As a result, a voltage larger than a predetermined power supply voltage (e.g., 5V) is output to the load coupled with the power output terminal 15.